1. Field of the Invention
The present invention generally relates to a semiconductor device.
Priority is claimed on Japanese Patent Application No. 2011-086715, filed Apr. 8, 2011, the content of which is incorporated herein by reference.
2. Description of the Related Art
FIG. 20 is a cross-sectional view illustrating a schematic configuration of a semiconductor device in the related art. A semiconductor device 1p shown in FIG. 20 is a stack-type semiconductor device of a chip-on-chip (CoC) type.
The semiconductor device 1p includes a wiring board 2 and a chip stacked body 3p mounted on one surface of the wiring board 2. The chip stacked body 3p includes a plurality of memory chips 31pa to 31pd and an interface chip 32p. Each of the memory chips 31pa to 31pd and the interface chip 32p includes a surface bump electrode 311 and a rear bump pad 312 corresponding to the surface bump electrode 311, and the surface bump electrode 311 and the rear bump electrode 312 are electrically connected by a through electrode 4. The plurality of memory chips 31pa to 31pd and the interface chip 32p are electrically connected to each other via the surface bump electrode 311, the rear bump electrode 312, and the through electrode 4.
In addition, the surface bump electrode 311 of one surface (a lower-side surface in FIG. 20) of the interface chip 32p is connected to an electrode pad 23 of the wiring board 2.
An assembly process of the semiconductor device 1p shown in FIG. 20 will be described. FIG. 21 is a view for explaining an assembly process.
As shown in FIG. 21, the memory chip (a second-level semiconductor chip) 31pb is stacked and mounted on the memory chip 31pa held on a level 99.
Each of the memory chips 31pa to 31pd and the interface chip 32p includes a surface mark and a rear mark in a surface side and a rear surface side of the chip, respectively. The surface mark and the rear mark are used for alignment when semiconductor chips are stacked. Specifically, the surface mark of the memory chip 31pa is photographed by a board-side recognition camera of a flip chip bonder and a coordinate of the memory chip 31pa on the level is recognized. The rear mark of the memory chip 31pb picked up by a tool BT of the flip chip bonder is photographed by a part-side recognition camera of the flip chip bonder and a coordinate of the memory chip 31pb on the tool is recognized. According to the obtained position information, a position of the tool is adjusted with respect to the level and the memory chip 31pb is stacked and mounted on the memory chip 31pa so that the surface bump electrode 311 of the memory chip 31pa and the rear bump electrode 312 of the memory chip 31pb accurately overlap.
Similarly, the memory chips (third- and fourth-level semiconductor chips) 31pc and 31pd and the interface chip 32p (fifth-level semiconductor chip) are stacked and mounted.
As described above, the surface mark and the rear mark are employed to perform accurate alignment between the semiconductor chips.
FIG. 22 is a cross-sectional view of a mark portion of a memory chip 31p. 
As shown in the cross-sectional view of FIG. 22, the memory chip 31p includes a multi-layer wiring structure including wiring tungsten WT and first to third aluminum wirings 1ALp, 2ALp, and 3AL.
In addition, as shown in FIG. 22, a surface mark 313 including the third aluminum wiring 3AL is formed in a surface side of the memory chip 31p and the wiring tungsten WT connected to a through electrode TSV (through-silicon via) for a rear mark is formed below the surface mark 313. A rear bump electrode 312 is further connected to the through electrode TSV for a rear mark, and the through electrode TSV for a rear mark and the rear bump electrode 312 form a rear mark 314. The through electrode TSV for a rear mark penetrates a semiconductor substrate 319.
In addition, a polyimide film PI is formed on the multi-layer wiring structure. The polyimide film PI has a PI opening PIO formed in an area including a portion on the surface mark 313.
In a recent semiconductor process, chemical mechanical polishing (CMP) technology is used for planarization. In general, in order to correct a difference in polishing state between a pattern-dense portion and a pattern-sparse portion in the CMP process, a dummy pattern may be arranged in the sparse portion. The CMP dummy pattern includes a minute pattern such as the first and second aluminum wirings, the wiring tungsten, gates, and shallow trench isolations STI in either side of the PI opening.
In the related art, the dummy pattern is mostly prohibited from being arranged below the PI opening PIO due to the following two reasons. First, there is a case in which the minute dummy patterns of wiring layers of the first and second aluminum wirings become an obstacle in recognition of the surface mark 313 of the third aluminum wiring 3AL. Second, when the minute pattern such as a gate is present below the surface mark, there is a case in which the gate of the minute pattern serves as a hard mask and causes occurrence of particles in a dry etching process of the through electrode TSV for a rear mark since the through electrode TSV for a rear mark is below the wiring tungsten pad WTP.
Therefore, a prohibition area PA is provided even in a portion of the surface mark described herein. In addition, in FIG. 22, the CMP dummy pattern prohibition area PA almost corresponds to the PI opening PIO (to be described in detail later).
It has become clear from the inventor's research that in the assembly process, contrast of the surface mark 313 is significantly degraded in recognition of the surface mark 313 through the recognition camera when the chip itself is embedded in the stack semiconductor device.
FIG. 23 is a cross-sectional view illustrating a PI opening PIO in which incident light (a solid line) and reflected light (a dashed line) of lighting are indicated. Since only a dielectric material such as silicon oxide (SiO2) is present in the PI opening PIO over a pad of wiring tungsten WT, attenuation of visible light is very small. Thus, reflection from a wiring tungsten pad WTP, which is a background of a surface mark 313, is large and contrast of the surface mark 313 is significantly degraded.
As a result, there is a problem that a recognition error of the surface mark 313 occurs in a TSV stacking process and a throughput of the above-described assembly process is considerably degraded.
Documents related to the above-described technical content include Japanese Patent Laid-open Publication No. 2006-140300 and Japanese Patent Laid-open Publication No. 2007-088124.
Japanese Patent Laid-open Publication No. 2006-140300 discloses that when a multilayered circuit pattern is formed on a semiconductor substrate, with respect to an accuracy measurement mark for inspecting whether a resist pattern formed by exposure accurately overlaps a circuit pattern of an underlying layer, a dummy pattern is formed in a mask formation area of an underlying wiring layer below the wiring layer in which a main scale pattern is formed, in order for the main scale pattern not to be affected by dishing during CMP.
Japanese Patent Laid-open Publication No. 2007-088124 describes an alignment mark of a mounting board.
Japanese Patent Laid-open Publication No. 2006-140300 thoroughly discloses only the accuracy measurement mark merely used for alignment of the resist pattern when forming a device forming layer. Therefore, Japanese Patent Laid-open Publication No. 2006-140300 does not describe recognition of an alignment mark after forming a semiconductor chip at all or a mark symmetrically arranged with respect to the accuracy measurement mark, and does not relate to a semiconductor chip of a stack semiconductor device.
Japanese Patent Laid-open Publication No. 2007-088124 discloses only the alignment mark when a device is mounted on a flexible board and does not relate to a semiconductor chip of a stack semiconductor device.